Qualifications:   

• BS/MS in Electrical Engineering or Computer Science/Engineering
• 8+ years logic design experience as a part of either CPU, Cache, Fabric, Digital Power Management, DVFS, Sensors, PCMs, Debug, Peripherals and/or SoC development
• 5+ years of Management Experience
• Knowledge of logic design flow including RTL coding, Synthesis, timing constraints, timing closure.
• Demonstrated expertise in Computer Architecture, Digital Design, IP/SoC design principles as part of SoC and/or IP development.

Additional Preferred Qualification:

• Highly Proficient in Verilog/System Verilog coding constructs.
• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
• Demonstrated experience and knowledge of clock crossings, and power/UPF in design
• Ability to write scripts using Perl, Tcl, Python etc.
• Familiarity with Industry standard interface protocols is a plus.
• Familiarity with Formal Equivalence Verification and Power Analysis is a plus.
• Excellent verbal and written communication skills.