Qualifications

• BS and/or MS in Electrical Engineering or equivalent degree

• 8+ years of RTL design and/or architecture experience

• Knowledge of DMA engine, hardware offloading, programmable logic. Prior experience in designing Accelerator engines is a plus.

• Proven track record with the definition and development of complex SoCs. In depth understanding of processors and peripheral interconnect bus protocols and architectures

• High performance (low latency, high bandwidth) design techniques

• Understanding of low power microarchitecture techniques. Strong knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis

• Self-motivated and able to work effectively both independently and in a team.