Hey Guys, I have an opening to share with you.

We are looking for experienced FPGA Verification Engineer.

As an FPGA Verification engineer, you will be responsible for designing verification plan, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up.

Roles & Responsibilities:

• Must have 3-10 years of experience in developing System Verilog UVM based test environments, developing and implementing test plans – at block, sub-chip and chip levels.
• Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools.
• Exposure to UVM (or similar) verification methodologies is required.
• Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired.
• Working knowledge on HW (board or equivalent platform) is preferred. Working knowledge of RTL design is preferred.
• Should be conversant with technologies like, Ethernet, PCIe etc. Knowledge of telecom protocol is preferred.
• Structured and thorough with analytical and troubleshooting skills.
• Good written and oral communication skills are required.
• Flexible, innovative, self-driven and willing to take own initiatives.

If this is interesting for you then please share your resume while applying. Also, please feel free to reach out in case of any queries.

Thanks,

Apoorva Srivastava