Job Description
Job Description In this position you will be responsible for STA including timing analysis, noise glitch analysis for leading-edge IP designs. Your responsibilities include but are not limited to: Timing execution and convergence including setup, hold, burn-in, noise, timing budgeting and efficient timing closure for DDR/ PCIe/ High Speed Serial IOs/ Type-C/ USB/ Ethernet PHYs Work closely with process technology team to understand process characteristics and set appropriate constraints in timing analysis flows and methodology. Interact with SoC customers to understand IP/SoC interface design requirements/objectives and develop appropriate interface signoff constraints for IPs. Mentor junior design engineers to build a capable team.
QualificationsBTech or Mtech with 15+ years of experience in relevant field Experience of STA/ timing convergence of high frequency designs. Additional qualifications include hands-on expertise and experience in block level and top level Static Timing Analysis using Synopsys Primetime or equivalent commercial tool, timing constraints generation and management, and timing convergence. Expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules on 7nm or smaller process required Understanding of process variation effects, and experience in variations analysis and convergence mechanism would be a plus. Expertise and in-depth knowledge of industry standard EDA tools (Timing, Synthesis, P&R) and ASIC design flow is required. Experience in timing and power signoff methodology development, timing corners/modes definition would be a big plus. Clocking/Physical design and synthesis exposure would be plus point Proficiency in scripting language, such as, Perl & Tcl required.
Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
Bangalore, KA, IN
