Job Description

Are you passionate about disrupting the industry with your innovation? Working with a diverse group? Influencing the outcome? If so, then XSE (Xe Silicon Engineering) Organization has an opportunity for you. We are responsible for delivering industry-leading GPU (3D, media, compute, and display) hardware, intellectual property (IP) blocks and system-on-a-chip (SoC) products for discrete graphics and throughput computing. We strive to lead the industry through continuous innovation and world-class engineering. We work closely with partners across Intel and we are looking for a Lead Networking IP Designer to join our team. In this position, the candidate would play a senior Technical Leadership role in the Microarchitecture and Logic Design for Discrete Graphics IP and SoC development within XSE. The candidate is expected to actively collaborate and drive the development of Micro-architecture specifications and the design implementation for Discrete Graphics IP and SoCs. Candidate responsibilities include the following: � All phases of frontend microarchitecture and RTL design for a Networking IP targeting high frequencies. � Understanding of the SOC and system architecture to be able to debug SOC and PostSi issues. � Work with architects on feature scoping and approvals, feasibility studies, design tradeoff analysis � Design and Testplan Reviews of your design, understand the inter-operability with interfacing designs. � Understand the physical design implementation and challenges, work very closely with Physical Design for timing closure/clocking issues � Close collaboration with planning teams, architects, validation, physical design, PostSi bringup teams. Behaviour traits that we are looking for: � Excellent both written and verbal communication skills � Proactive drive to achieve high-quality results through strong team-work � Innovative thinker to drive solutions to complex cross-functional technical problems working with senior technical peers/partner organizations � Flexibility to work in a dynamic environment and seamlessly multitask

Qualifications� You must possess a minimum of Bachelor Degree in Computer Engineering, Computer Science or Electrical Engineering with 15+ years of industry experience. � 10+ years of experience in high performance digital logic designs and integration, timing analysis and closure for high frequency designs. � Strong understanding of networking architecture, RTL design flows and debug skills, STA and Physical design exposure to be able to close the high frequency targets. � Proficient in RTL design using Verilog/System Verilog � Knowledge in industry FE/RTL tools and design, timing closure methodologies � Good communication and collaboration skills. � Ability to work independently and proactively to lead technical activities

Inside this Business Group

Intel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution level—not just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.

Other LocationsIndia, Hyderabad

Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....

Legal Disclaimer:

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Bangalore, KA, IN