Job Description

The IPG IP Engineering Group is looking for energetic and passionate Logic Design leader. You will work on high-speed digital design targeted towards low power optimized IP implementations. You will be responsible for Overseeing definition, design, verification, leading small RTL design team & your responsibilities will include but are not limited to- implementing RTL in System Verilog, setting up Automation flows for IP Logic Design , ensuring RTL quality via Front End tools like Lint, CDC, VCLP, Synthesis QA checks etc, creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to help Logic Design in areas like Coverage closure, timing convergence etc. You will also have an opportunity to work on ensuring the RTL quality of IP is high and will contribute to automating various Front End Tool, Flows and Methods. You will be able to utilize your scripting skills to innovate the IP RTL delivery to Validation teams, Backend Teams as well as SoC teams. The ideal candidate should exhibit behavioral traits that indicate: Excellent written and verbal communication skills are critical on a small, fast-moving team. As part of a growing, dynamic new business, the candidate must be successful working with many cross functional teams and manage multiple tasks and changing requirements, in an innovative environment.

Qualifications

The successful candidate will possess a BS, MS degree with a minimum of 5 years of relevant industry experience.

Additional qualifications ideally include: Strong scripting skills, experience in working with Front End design tools, Synthesis, Low power design, understanding analog design concerns and driving to an optimal solution between analog and digital designs, familiarity with pre-silicon and post-silicon validation.

Experience in the following areas/ skills are desired:

• DDR Design domain knowledge
• Strong communicator and proven leadership experience.
• Git/Perforce/CVS know how
• Perl/Python/TCL
• Spyglass Lint, CDC, DFT, VCLP,
• Logic design using System Verilog
• Low-power design using UPF and clock gating
• Multiple clock domain design
• State machine design
• Simulation and debug experience using VCS/Verdi
• Synthesis and speed path debug

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Bangalore, KA, IN