Job Description

Responsibilities : In this position, the candidate will be responsible for design of soft IP cores for Intel's next generation chips (including SOCs) for the different market segments.

Qualifications:

Master of Science (or a Master of Technology) degree in Electrical Engineering with more than Eight years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than nine years of relevant industry experience.

Experience :

• Relevant ASIC design/validation experience in front end processes including RTL development, functional and performance verification
• Expertise in design, development and integration of design blocks (IP) for system-on-chip (SoC) components
• Expertise in verilog and system verilog based logic design
• Experience in synthesis flow and timing closure
• Experience in one/more of the following areas PCIe, I3C,USB, DP and /or AMBA standards (OCP, AXI, AHB etc..)
• Knowledge of SVA
• Knowledge of IO interconnect is a plus
• Looking for highly motivated individuals and ability to deal with ambiguity
• Knowledge of considerations for performance, power and cost optimization is desirable
• Ability to work in a team environment
• Ability to work with external technology companies for combined development of IPs / SOCs
• Experience in FPGA will be a plus

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Bangalore, KA, IN