Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Job Description

Develops pre-silicon functional validation tests to verify system will meet design requirements. Creates test plans for RTL validation defining and running system simulation models and finding and implementing corrective measures for failing RTL tests Analyzes and uses results to modify testing. The candidate will work as a member of a verification team / IP hybrid model solution playing a key leading role in developing SPBC IPs. Participates in the review of Architecture and Microarchitecture specifications for the Logic components. Provides IP integration support to SoC customers and hybrid model.

The responsibilities will include but not be limited to:

• Create review and signoff verification test plans.
• Drive participate in discussions across various disciplines to get a clear understanding of product features and their validation requirements.
• Develop the architecture and design of the verification environment in UVM.
• Development of test plans test bench BFMs checkers monitors trackers scoreboard and functional coverage.
• Develop run debug tests in SystemVerilog.
• Mentor other engineers in using the verification infrastructure and creating test benches.
• Ownership of verification of block/ cluster in SPBC and other IPs.
• Drive and participate in verification code functional coverage RTL code coverage reviews and provide implement feedback across the project.
• Contribute to the development and maintenance of long-term design verification strategy.
• Track progress of the block/ cluster owned to achieve goals timely.
• Provide indicators and guidance to management on issues and roadblocks on a timely basis.
• Be able to work with teams across org/ geos.
• Should be able to contribute as IC or technically leading a group of team.
• Hands-on knowledge working in hybrid environment (Virtual platform / RTL)
• Experience in integration and debugging hybrid environment which includes multiple components (Virtual Platform / RTL / FW)
• Integration and validation of 3rd party IPs on Intel's native environment

Qualifications

• BE/BTech or ME/MTech 7-9 years of domain experience out of which at least 5 years of hands-on IP verification experience using SV and UVM
• Proficiency in SV, UVM, and object-oriented programming
• Strong understanding of engineering design principles
• Proven track record in IP verification from environment development to tests development to validation closure
• Experience Relevant ASIC design validation experience in front end processes including RTL functional performance and power verification
• Expertise in verification of design blocks IP for system-on-chip SoC components
• Excellent written and verbal communication skills
• Expertise in verification of design blocks IP for system-on-chip SoC components
• Very good at creation of test plans schedules and cost estimates for design verification efforts
• Experience in the development and deployment of verification strategies and methodologies across teams and organizations
• Apart from simulation should have work experience with at least one other verification aspect like formal verification, gate Level verification, etc.
• Proficiency in scripting languages and utilities including Make Perl Python etc.
• Expert-level knowledge of simulation tools such as VCS from Synopsys.
• Knowledge of industry-standard protocol such as SPI is a strong plus.
• Familiarity with Perl, C and shell scripts is a plus.
• Strong skills in communication, initiative, promote innovation and collaboration.
• Highly motivated to learn and adapt to fast-evolving technologies and environments.
• Responsible for understanding architecture spec and deriving test cases test plans
• Need to be a key team player while being highly energetic and motivated independent and self-driven with minimal mentoring handholding
• Expected to help drive in throughput test case setup, analysis report of the DUT
• Expected to define functional coverage code hit it through sequence enhancement and newer directed test cases