Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Job Description

• Perform logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units for PLLs.
• Participate in the development of Architecture and Microarchitecture specifications for the Logic components.
• Provide IP integration support to SoC customers and represents RTL team.
• Work on high-speed digital design and is targeted towards low power optimized implementations of high speed PLLs
• Implement RTL in System Verilog, validating the design through functional sims and take it through FE flows.

Qualifications

• Candidate must have a Bachelor's degree in Electrical Engineering and 4+ years' experience or a Master's degree in Electrical Engineering and 3+ years' experience

Required Qualifications:

• RTL level Digital IC Design using System Verilog and/or Verilog Low power design,
• Analog design concerns and driving to an optimal solution between analog and digital designs
• Pre-silicon and post-silicon validation

Preferred Qualifications:

• Prior experience in/with:
• Logic design using System Verilog
• Low-power design using UPF and clock gating
• Multiple clock domain design
• Exposure to LINT, CDC, LEC, timing/synthesis
• Exp in Regression, code coverage, GLS etc.