Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Job Description

This position is for a leadership role in an exciting new group in Intel India You will be involved in development of leading edge Intellectual Property cores that will power next generation systems for our customers around the world Performs logic design Register Transfer Level RTL coding and simulation to generate cell libraries functional units and subsystems for inclusion in full chip designs Participates in the development of Architecture and Microarchitecture specifications for the Logic components Provides IP integration support to SoC customers and represents the IP team

Qualifications

• Bachelors Degree in Electrical Engineering with 8 years of experience or Masters Degree in Electrical Engineering or Computer Engineering with 6 years of experience on ASIC or FPGA hardware IP design and verificationo
• In depth knowledge with Verilog System Verilog RTL design FPGA design and FPGA design tools
• In depth knowledge of high speed serial protocols CXLPCIeEtherneto
• Good programming skills C C perl python tcl etc
• Capable of building block and system level testbench from scratch using System Verilog experienced in UVM constrained random coverage driven concepts assertion based verification and functional coverage techniqueso
• In depth knowledge and experience in UVMVMMOVM
• Experience in Design and verification tools simulation tools and debug tools
• Endtoend System level experience including design software firmware and hardware
• Proactive selfmotivated and quick learner
• Good team spirit and ability to deliver to schedule
• Excellent analytical and problem solving skills
• Strong verbal and written communication skills
• Ability to multitask and work in a dynamic environment
• Must have experience working closely with customers understanding their systems and providing optimized solutions